(1) Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory, (DRAM), device, and more specifically to a method of fabricating a DRAM device with a capacitor structure overlying a straight bit line shape.
(2) Description of the Prior Art
The attainment of high density DRAM devices has been limited by the inability of the semiconductor industry to provide the capacitor structures, needed for large scale DRAM integration. The limited area allotted for the capacitor structure has led to novel capacitor designs, targeted at increasing capacitor area, and thus increasing capacitance. One method of increasing capacitor surface area, while still minimizing cell size, has been the use of a capacitor over bit line, (COB), cell structure, where a storage node of the capacitor is formed upon a bit line. The use of the COB technology removes the limitation of the capacitor structure being placed in non-bit line regions, allowing capacitor structures with larger area, thus larger surface area and larger capacitances, to be used for DRAM devices.
This invention will describe a process for fabricating a COB structure in which a straight bit line shape is used. The straight line bit line shape consumes less area than multi-shaped COB structures, and also allows smaller photolithographic shapes to be achieved, thus allowing DRAM density increases to be realized. This invention will also provide a process for forming a storage node contact hole, through a narrow, straight bit line shape, to an underlying polysilicon contact plug structure, which in turn is in contact with a source and drain region of a transfer gate transistor, followed by passivation of the storage node contact hole, prior to forming the storage node contact structure. This process sequence also allows increased DRAM density to be obtained. Prior art, such as Koh, et al, in U.S. Pat. No. 5,627,095, describe a method for fabricating a DRAM structure, using novel techniques for forming bit lines and capacitor structures, however that prior art does not offer the process used to obtain the DRAM density improvements achieved in this invention via the use of a straight bit line shape, and a storage node contact hole, through a straight bit line shape.